1. Field of the Invention
The present invention relates to a semiconductor substrate manufacturing method and, more particularly, to a manufacturing method which improves film thickness precision of each layer of a semiconductor substrate having a dielectric isolating structure.
2. Description of the Related Art
In a semiconductor integrated circuit, various types of isolating structures are generally used to electrically isolate circuit elements so that the circuit elements do not interfere with each other.
An example of such an isolating structure is a dielectric isolating structure in which surfaces (the outer circumferential surfaces and the bottom surface) of a circuit element are perfectly surrounded by a predetermined dielectric so as to be isolated like an island (to be referred to as an isolated island hereinafter) from other circuit elements.
In this dielectric isolating structure, an insulating layer serving as a dielectric isolating layer of a bottom surface portion for electrically isolating a circuit element from other circuit elements is formed on a semiconductor substrate, and high- and low-concentration n-type silicon layers serving as circuit element regions are sequentially formed on the insulating layer. A trench-like groove is formed to perfectly surround the outer circumferential surfaces of the circuit element region and to extend from the outer circumferential surfaces of the circuit element region to the insulating film. An insulator is filled in the trench-like groove to form a trench isolation for isolating the circuit element from other circuit elements.
The bottom surface (bottom surface of an isolated island) of the circuit element region, therefore, is isolated by the insulating layer, and the trench-like groove in which an insulator is filled is formed around the circuit element region, thereby isolating the circuit element from other circuit elements.
In the manufacture of a circuit element region having the dielectric isolating structure described above, the insulating layer formed on the bottom of the insulation island or the conductive layer serving as a current path should have a precise thickness. This is because the characteristic and performance of the circuit element are determined by the thickness of the insulating layer or that of the conductive layer. In order to form an insulation layer or a conductive layer, having a sufficiently precise thickness, several conditions, must be satisfied.
First, the film thickness of the low-concentration n-type silicon layer must be uniform. An error of this uniformity preferably falls within the range of .+-.10%. That is, if a predetermined thickness is 1.5 .mu.m, for example, an error is preferably .+-.0.15 .mu.m or less.
Second, a sheet resistance of the high-concentration n-type silicon layer must be uniform. An error of this sheet resistance preferably falls within the range of .+-.15%. For example, an error is preferably .+-.3 .OMEGA..quadrature. or less with respect to a predetermined value of 20 .OMEGA./.quadrature..
Third, since the side surfaces of the isolated island are perfectly surrounded by an insulator, this structure can be manufactured more easily when the groove for receiving the insulator is shallow. Therefore, the total film thickness of the high- and low-concentration n-type silicon layers is preferably small in order to form the dielectric isolating film in the lateral direction. That is, the film thickness is preferably 5 .mu.m or less.
Conventional manufacturing steps of a general dielectric isolating structure will be described below. A first conventional manufacturing method is shown in FIGS. 11A to 11C.
In an n.sup.+ -type impurity diffusing step shown in FIG. 11A, a high-concentration n.sup.+ -type impurity is diffused in a low-concentration n-type silicon substrate 1 serving as a first silicon substrate, thereby forming a high-concentration n-type silicon layer 2. In an adhering step shown in FIG. 11B, the two surfaces of the first silicon substrate are oxidized to form silicon oxide (SiO.sub.2) films 3. In addition, a second silicon substrate 4 is bonded to the SiO.sub.2 film 3 at the silicon layer 2 side. In a polishing step shown in FIG. 11C, the resultant structure is polished from the side of the low-concentration n-type silicon substrate 1 of the bonded first and second silicon substrates to have a predetermined thickness.
A second conventional manufacturing method is shown in FIGS. 12A to 12C.
In an adhering step shown in FIG. 12A, the two surfaces of a high-concentration n-type silicon substrate 5 serving as a first silicon substrate are oxidized to form silicon oxide films 6. A second silicon substrate 7 is bonded to the silicon oxide film 6. In a polishing step shown in FIG. 12B, the resultant structure is polished from the side of the high-concentration n-type silicon substrate 5 of the bonded first and second silicon substrates to have a predetermined thickness with reference to the bonded surface. In an epitaxial growth step shown in FIG. 12C, a low-concentration n-type silicon film 8 is formed by epitaxial growth on the high-concentration n-type silicon substrate 5 of the silicon substrate having the predetermined thickness.
A third conventional manufacturing method is shown in FIGS. 13A to 13E.
In an epitaxial growth step shown in FIG. 13A, a low-concentration n-type silicon film 10 is formed by epitaxial growth on a high-concentration n-type silicon substrate 9 serving as a first silicon substrate. In an adhering step shown in FIG. 13B, the two surfaces of a substrate constituted by the silicon substrates 9 and 10 are oxidized to form silicon oxide films 11. A second silicon substrate 12 is bonded to the silicon oxide film 11 at the silicon film 10 side. Thereafter, the bonded silicon substrates are annealed in a nitrogen/oxygen gas atmosphere. The resultant structure is dipped in a fluoric acid solution to remove the silicon oxide film 11 at the high-concentration n-type silicon substrate 9 side.
In a selective etching step shown in FIG. 13C, an etching solution having a high etching selectivity with respect to high-concentration n-type silicon is used to selectively etch and remove only the high-concentration n-type silicon substrate 9. In an n.sup.+ -type impurity diffusing step shown in FIG. 13D, a high-concentration n.sup.+ -type impurity is diffused in the low-concentration n-type silicon film 10 of the etched silicon substrate. In an epitaxial growth step shown in FIG. 13E, a low-concentration n-type silicon film 13 is epitaxially grown on the n-type silicon film 10 now having a high concentration. Note that this structure can be similarly manufactured by using a p-type silicon substrate instead of the n-type silicon substrate 9.
The following problems are posed, however, in the manufacture of a circuit element region using a dielectric isolating structure by any of the above conventional manufacturing methods.
That is, even a silicon substrate (e.g., a 125 mm silicon wafer) considered to have a satisfactory flatness normally has thickness uniformity of about 1.0 .mu.m. In the polishing step of the above first conventional manufacturing method shown in FIG. 11C, therefore, if thin films are formed on the surfaces of a silicon substrate and the resultant structure is polished with reference to the rear surface (opposite surface) of the silicon substrate, it is difficult to polish the structure such that an error in uniformity of the film thickness of the low-concentration n-type silicon layer 1 falls within the range of .+-.10% of the film thickness, i.e., .+-.0.15 .mu.m or less throughout the entire surface of the silicon substrate.
In the second conventional manufacturing method, a predetermined film thickness can be obtained by removing a silicon substrate (a 125 mm silicon wafer) by polishing and performing epitaxial growth. Therefore, the total film thickness of the high- and low-concentration n-type silicon layers 5 and 8 can be set to be about 3.5 .mu.m.
In the polishing step shown in FIG. 12B, since the flatness of the silicon substrate represents thickness uniformity of about 1.0 .mu.m as described above, the uniformity in film thickness of the polished n-type silicon layer 5 is similarly degraded. As a result, the sheet resistance uniformity is lost to produce a difference of 24% to 34% according to sample data. In general, when an impurity concentration of a high-concentration n-type silicon film is about 5.times.10.sup.18 atm/cm.sup.3 or more, a film thickness cannot be measured because infrared rays for film thickness measurement cannot be transmitted. That is, it is sometimes difficult to polish the high-concentration n-type silicon layer 5 to have a predetermined thickness.
In the third conventional manufacturing method, the uniformity in film thickness and the sheet resistance of the high- and low-concentration n-type silicon layers can satisfy the above important conditions. When however, the low-concentration n-type silicon film 10 is epitaxially grown on the high-concentration n-type silicon layer 9 in the epitaxial growth step shown in FIG. 13A, particles of a reaction product or the like often bond to the surface of the silicon layer 9 to form undulations on the surface. If the surface is oxidized in this state to form the silicon oxide film 11 and the silicon substrate 12 having a mirror-like adhesion surface is bonded to the silicon oxide film 11, cavities may be formed between the adhesion surfaces.
In addition, since the above epitaxial growth step requiring higher cost than those of the other manufacturing steps is repeatedly performed twice, the manufacturing cost is rather increased, and the manufacturing steps are complicated. For these reasons, the third convention manufacturing method is not preferable as a mass-production method.
As another isolating method, in an isolating structure using an isolation diffusion layer formed by p-type impurity diffusion, a junction capacitance is present in a formed transistor to prevent a high operation speed of a circuit element. In addition, since an isolated island is isolated from other circuit elements by the isolation diffusion layer, the width of an isolating layer becomes larger than that obtained when an insulator is used, thereby limiting the degrees of micro-patterning and integration.